1. FIELD OF THE INVENTION:
The present invention relates to the field of timing systems, and more particularly to a digital timing loop for slave clock systems.
2. ART BACKGROUND:
Many large electronic systems require extremely accurate clock signals to operate correctly. In order to generate these extremely accurate clock signals, a very stable oscillator such as a cesium or hydrogen maser is typically used. These masers provide clock signals that are accurate within the range of 1 part in 10.sup.13 to 1 part in 10.sup.14.
In large systems, there are often several clocks to provide the necessary timing signals. These clocks may be dispersed over large distances and connected together in a network. One of the clocks in the network typically acts as a master unit and the remaining clocks are slave units. While the slaves are connected to the master, they closely track the output master clock signal to insure that all parts of the system are synchronized. Should the master clock fail, however, the slave clocks must be able to generate highly accurate timing signals of their own, and their circuits must rely on the slave clock signals until the master clock is restored.
In prior art devices, slave clocks were comprised of analog oscillators. The output frequency was adjusted by providing an error voltage to the oscillator. However, these analog oscillators are not highly accurate when compared to an atomic reference clock. In order to generate a clock signal that is accurate to 1 part in 10.sup.14, the error voltage must be equally as accurate. Prior art technology was simply unable to achieve this high degree of precision.
Another disadvantage of the prior art is the speed in which the frequency of the slave clock may be changed. Analog devices must be designed to respond either quickly (within milliseconds) or slowly (within seconds) to an error signal. Thus, the prior art devices were not able to adapt or change the response time to account for changes in the application of the clock system. If the response time is too fast, transient events will introduce errors in timing. If the response time is too slow the clock system may take too long to stabilize after acquiring the master clock reference frequency.